Mandelbrot Explorer
A fun little demo of some game-changing technologies
What is it?
This Mandelbrot fractal explorer is a demonstration and development vehicle for emerging technologies, including:
- Cloud FPGAs
- Hardware-accelerated web applications
- Advanced hardware modeling in Transaction-Level Verilog
Enable Hardware Acceleration
The true showcase is enabled by special hardware acceleration technology, called cloud FPGAs. We use these to accelerate the Mandelbrot calculations by ~20x! This specialized hardware isn’t cheap, though, so we do not provide it here, but we enable you to provide your own. It is not for the faint of heart, but we’re doing our best to make it easier. You can find more information from the open-source repository.
Cool Technologies
Cloud FPGAs:
Field Programmable Gate Arrays (FPGAs) are chips containing millions or billions of logic gates that can be configured to perform any logic function. In contrast, Application-Specific Integrated Circuilts (ASICs) are designed and manufactured for a specific purpose. ASICs are optimized; FPGAs are flexible. And FPGAs are now available in the cloud, which is a huge enabler for open-source hardware!
Hardware Accelerated Web Applications:
Could FPGAs have great potential to accelerate compute infrastructure. But they are in their infancy. The barriers to entry are significant. This project is the development vehicle for an open-source framework for accelerating web applications (or services) using cloud FPGAs. The aim is to provide the communication layer by which a web application can communicate through standard web protocols, directly with hardware kernels running on cloud FPGAs. You are witnessing the first implementation of this infrastructure, or at least you would be if a cloud FPGA was attached.
Transaction-Level Verilog:
One of the biggest hurdles to ubiquitous hardware acceleration is the mere fact that hardware is not as easy to program as software. But new technologies are making it easier. This project utilizes advanced modern modeling techniques available in Transaction-Level Verilog (TL-Verilog). You can learn about these techniques and try them for yourself at makerchip.com.
Contribute!
This is a group effort. It’s tons of fun, it’s charting new territory, and it’s got something to offer everyone. You could:
- Improve the website.
- Enhance the algorithms.
- Optimize the hardware kernel.
If you are a student, Google Summer of Code might be a great opportunity to get involved.
Feel free to contact the authors, or browse the project on github.
Donate
Sorry, we do not have a donation system in place, yet. But, let us know you care. If there is enough interest we will make it possible to sponsor cloud FPGA time in your name.